Embodiments of the invention relate to a liquid crystal display array substrate and a manufacturing method thereof.
Thin film transistor liquid crystal displays (TFT-LCDs) are an important type of flat panel displays (FPDs).
TFT-LCDs can be classified into a vertical electrical field type and a horizontal electrical field type depending on the direction of the electrical field by which the liquid crystal is driven. For a vertical electrical field type TFT-LCD, a pixel electrode is formed on an array substrate while a common electrode is formed on a color filter substrate. For a horizontal electrical field type TFT-LCD, both a pixel electrode and a common electrode are formed on an array substrate. Therefore, an additional patterning process for forming the common electrode is required when a horizontal electrical filed type TFT-LCD array substrate is manufactured. A vertical electrical field type TFT-LCD comprises a twist nematic (TN) type TFT-LCD. A horizontal electrical field type TFT-LCD comprises a fringe field switching (FFS) type TFT-LCD and an in-plane switching (IPS) type TFT-LCD. A horizontal electrical field type TFT-LCD, especially an FFS type TFT-LCD, has advantages such as wide view angles and high aperture ratio and have been widely used in practice.
Currently, an FFS type TFT-LCD array substrate is manufactured by forming structural patterns via a plurality of patterning processes. Each patterning process comprises processes such as masking, exposing and developing of photoresist, etching and removing remaining photoresist. An etching process comprises a dry etching process or a wet etching process. Therefore, the complexity of a method for manufacturing a TFT-LCD array substrate can be evaluated based on the numbers of the employed patterning processes, and reducing patterning processes means decreasing manufacturing cost. A conventional six-patterning process for an FFS TFT-LCD array substrate can comprise: patterning for a common electrode, patterning for a gate line and a gate electrode, patterning for an active layer, patterning for source/drain electrodes, patterning for a through hole, and patterning for a pixel electrode.
In addition, for example, a conventional four-patterning process for manufacturing an FFS TFT-LCD array substrate comprises the following steps.
Step 1, depositing a first metal film, and forming a gate line, a common electrode line and a gate electrode by a first patterning process with a normal mask.
Step 2, depositing a gate insulating film, an active layer (including a semiconductor layer and a doped semiconductor layer) film, and forming an active layer by a second patterning process with a normal mask.
Step 3, depositing a first transparent conductive film and second metal film sequentially, and forming a pixel electrode, a source electrode, a drain electrode and a TFT channel by a third patterning with a dual tone mask.
Step 4, depositing a passivation layer and a second transparent conductive layer, forming a passivation layer connection hole, PAD region connection holes and a common electrode, wherein the passivation layer connection hole is used for connection between the common electrode and the common electrode line, a PAD region is a region where leads of a driving circuit board are pressure welded with the array substrate, and electrically connected with the gate line, the data line and the common electrode line on the array substrate via the PAD region connection holes.
An array substrate of an FFS type liquid crystal display manufactured by the above described four-patterning method is characterized in that the common electrode can cover the whole substrate since it is formed in the last step. That is to say, the common electrode is formed above the pixel electrode and also above the signal lines (the gate line, the data line and the common electrode line).
While, for an array substrate of an FFS type liquid crystal display manufactured by the conventional six-patterning method, the common electrode cannot cover the whole substrate and is only formed below the pixel electrode since the common electrode is formed in the first step before forming the gate line and is not electrically connected with the gate line.
According to the array substrate of the FFS type liquid crystal display manufactured by the above four-patterning method, it has a larger aspect ratio when compared with the array substrate of the FFS type liquid crystal display manufactured by the above six-patterning method.
An aspect ratio is determined by an area blocked by a black matrix on a color filter substrate, and the black matrix is provided to block a region over and around the signal lines where the liquid crystal molecules are rotated abnormally.
When the liquid crystal is driven in a TFT-LCD, disturbing electrical fields is formed around the signal lines. Among these disturbing electrical fields, the electrical filed between the common electrode above the pixel electrode and a signal line is the most harmful. The electrical field lines of the electrical field will disturb the rotation of the liquid crystal molecules above the pixel electrode (belonging to the liquid crystal molecules used for normal displaying) so that the image cannot be displayed correctly. In this case, the liquid crystal region that is disturbed should be blocked by a black matrix. Therefore, the more the disturbance, the smaller the aspect ratio.
However, for the array substrate of the FFS type liquid crystal display manufactured by the above four-patterning method, since there is the common electrode above the signal lines, electrical field will be generated between the signal lines and the common electrode thereabove, so that electrical field lines are concentrated in the regions above the signal lines, and the electromagnetic effect between the signal lines and the common electrode above the pixel electrode is weakened. Therefore, the area where the liquid crystal molecules are disturbed around the signal lines is decreased accordingly. Thus, the area blocked by the black matrix will be reduced and the aspect ratio is increased accordingly.
FIG. 8 is a schematic plan view of an array substrate of an FFS type liquid crystal display with a high aspect ratio. FIG. 9a is a cross-sectional view of FIG. 8 taken along line A-A, and FIG. 9b is a cross-sectional view of FIG. 8 taken along line B-B.
As shown in FIGS. 8, 9a and 9b, the conventional FFS type TFT-LCD array substrate mainly comprises a transparent substrate 10, a gate line 1, a gate insulating layer 11, a data line 2, a thin film transistor (TFT) 3, a pixel electrode 4, a common electrode line 5, a common electrode 6, a passivation layer 12′ and etc. Specifically, the gate line 1 and the common electrode line 5 are provided transversely on the transparent substrate 10, and the gate insulating layer 11 covers the gate line 1 and the common electrode line 5. The data line 2 is provided on the gate insulating layer 11 longitudinally. The TFT 3 is provided at the intersection of the gate line 1 and the data line 2. The drain electrode of the TFT 3 is connected with the pixel electrode 4, and the pixel electrode 4 is a plate-like electrode. The passivation layer 12′ is formed on the pixel electrode 4, the TFT 3, the data line 2 and the gate insulating layer 11. The common electrode 6 is formed the passivation layer 12′. The common electrode 6 is a slit electrode with slits 63. The common electrode 6 is connected with the common electrode line 5 via a connection hole 53 in the passivation layer 12′.
The gate line 1 is used to provide an “ON” signal to the TFT 3, and the data line is used to provide a data signal to the pixel electrode 4. The TFT 3 is an active switching element. The common electrode line 5 is used to provide a common signal to the common electrode 6. After the gate line 1 provides an “ON” signal to the TFT 3, the data signal from the data line 2 can be inputted into the pixel electrode 4 via the TFT 3, thus an electrical filed for driving the liquid crystal is generated between the pixel electrode 4 and the common electrode 6.
In the above structure, the common electrode is formed above the signal lines, and the aspect ratio is increased. But, if the distance between the signal lines and the common electrode is too small, that is to say, the thickness between the signal lines and the common electrode is too thin, the electrical field formed between the common electrode and the signal lines will disturb the signals from the signal lines, which leads to signal delay and affects the display quality disadvantageously.
For example, in an array substrate of an FFS type liquid crystal display manufactured by the above six-patterning method, the thickness of the passivation layer is 2500 Å. However, in the array substrate as shown in FIGS. 8-9a, if the displaying performance same to that of the array substrate obtained by the above six-patterning method is reached, the thickness of the passivation layer needs to be 6000 Å.
Currently, not only a high aspect ratio but also low power consumption characteristic is demanded in the liquid crystal display field. Especially for the liquid crystal display used in the notebook computer, the low power consumption attracts much attention. However, for the FFS type TFT-LCD array substrate with a high aspect ratio, although the aspect ratio is increased, the too thick passivation layer leads to a large distance between the common electrode and the pixel electrode, thus, a higher driving voltage is needed for a normal operation and the power consumption is increased notably.
However, similarly to the FFS type TFT-LCD array substrate, the passivation layer in the conventional TN type TFT-LCD array substrate also has a uniform thickness in the regions corresponding to the pixel electrode, the gate line and the data line for each pixel region. As for the conventional TN type array substrate, the overlapping portion of the pixel electrode and the common electrode line is formed into a storage capacitor, forming a structure of storage on common. The thicker the passivation layer between the pixel electrode and the common electrode line, the smaller the storage capacitance.